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The Reduceron ReconfiguredNAYLOR, Matthew; RUNCIMAN, Colin.ACM SIGPLAN notices. 2010, Vol 45, Num 9, pp 75-86, issn 1523-2867, 12 p.Conference Paper

A scalable parallel reconfigurable hardware architecture for DNA matching : HARDWARE FOR BIOINFORMATICS APPLICATIONSSEGUNDO, Edgar José Garcia Neto; NEDJAH, Nadia; DE MACEDO MOURELLE, Luiza et al.Integration (Amsterdam). 2013, Vol 46, Num 3, pp 240-246, issn 0167-9260, 7 p.Article

Hardware implementation of subtractive clustering for radionuclide identification : HARDWARE FOR BIOINFORMATICS APPLICATIONSFARIAS, Marcos Santana; NEDJAH, Nadia; DE MACEDO MOURELLE, Luiza et al.Integration (Amsterdam). 2013, Vol 46, Num 3, pp 220-229, issn 0167-9260, 10 p.Article

A hardware architecture for subtractive clusteringSANTANA FARIAS, Marcos; NEDJAH, Nadia; DE MACEDO MOURELLE, Luiza et al.International journal of high performance systems architecture (Print). 2011, Vol 3, Num 2-3, pp 167-173, issn 1751-6528, 7 p.Article

A test-bench for the real-time project phase 2 of JETBATISTA, A. J. N; FERNANDES, H; SOUSA, J et al.Fusion engineering and design. 2004, Vol 71, Num 1-4, pp 83-88, issn 0920-3796, 6 p.Conference Paper

Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems : The SAFES Perspective : Configurable Computing Design-II: Hardware Level ReconfigurationGOGNIAT, Guy; WOLF, Tilman; BURLESON, Wayne et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 2, pp 144-155, issn 1063-8210, 12 p.Article

Partitioning methodology for heterogeneous reconfigurable functional unitsGALANIS, Michalis D; DIMITROULAKOS, Gregory; GOUTIS, Costas E et al.Journal of supercomputing. 2006, Vol 38, Num 1, pp 17-34, issn 0920-8542, 18 p.Article

CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable ArraysOLIVEIRA, Julio; MASEKOWSKY, Stephan; SCHWEIZER, Thomas et al.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 9, pp 1247-1259, issn 1063-8210, 13 p.Article

Scalable, wavelet-based video : From server to hardware-accelerated clientEECKHAUT, Hendrik; DEVOS, Harald; SCHELKENS, Peter et al.IEEE transactions on multimedia. 2007, Vol 9, Num 7, pp 1508-1519, issn 1520-9210, 12 p.Article

Parallel co-processor for PSODE MORAES CALAZAN, Rogério; NEDJAH, Nadia; DE MACEDO MOURELLE, Luiza et al.International journal of high performance systems architecture (Print). 2011, Vol 3, Num 4, pp 233-240, issn 1751-6528, 8 p.Article

Synthesis of regular expressions for FPGAsBISPO, Joao; CARDOSO, Joao M. P.International journal of electronics. 2008, Vol 95, Num 7, pp 685-704, issn 0020-7217, 20 p.Conference Paper

An EDF schedulability test for periodic tasks on reconfigurable hardware devicesDANNE, Klaus; PLATZNER, Marco.ACM SIGPLAN notices. 2006, Vol 41, Num 7, pp 93-102, issn 1523-2867, 10 p.Conference Paper

Frequent Item Computation on a ChipTEUBNER, Jens; MUELLER, Rene; ALONSO, Gustavo et al.IEEE transactions on knowledge and data engineering. 2011, Vol 23, Num 8, pp 1169-1181, issn 1041-4347, 13 p.Conference Paper

Reconfigurable hardware solution to parallel prefix computationJIN HWAN PARK; DAI, H. K.Journal of supercomputing. 2008, Vol 43, Num 1, pp 43-58, issn 0920-8542, 16 p.Article

Tartan : Evaluating spatial computation for whole program executionMISHRA, Mahim; CALLAHAN, Timothy J; CHELCEA, Tiberiu et al.ACM SIGPLAN notices. 2006, Vol 41, Num 11, pp 163-174, issn 1523-2867, 12 p.Conference Paper

High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable HardwareKASAP, Server; BENKRID, Khaled.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 5, pp 796-808, issn 1063-8210, 13 p.Article

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systemsGALANIS, Michalis D; MILIDONIS, Athanassios; KAKAROUNTAS, Athanassios P et al.Microelectronics journal. 2006, Vol 37, Num 6, pp 554-564, issn 0959-8324, 11 p.Article

Mixing static and dynamic strategies for high performance and low area reconfigurable systemsRUTZIG, Mateus Beck; SCHNEIDER BECK, Antonio Carlos.International journal of high performance systems architecture (Print). 2012, Vol 4, Num 1, pp 13-24, issn 1751-6528, 12 p.Article

FPGA Implementation of the N-FINDR Algorithm for Remotely Sensed Hyperspectral Image Analysis : SPACE TECHNOLOGYGONZALEZ, Carlos; MOZOS, Daniel; RESANO, Javier et al.IEEE transactions on geoscience and remote sensing. 2012, Vol 50, Num 2, pp 374-388, issn 0196-2892, 15 p.Article

Fault tolerance using dynamic reconfiguration on the POEtic tissueBARKER, Will; HALLIDAY, David M; THOMA, Yann et al.IEEE transactions on evolutionary computation. 2007, Vol 11, Num 5, pp 666-684, issn 1089-778X, 19 p.Article

The Promise of Reconfigurable Computing for Hyperspectral Imaging Onboard Systems: A Review and Trends : ADVANCES IN VERY-HIGH-RESOLUTION REMOTE SENSINGLOPEZ, Sebastian; VLADIMIROVA, Tanya; GONZALEZ, Carlos et al.Proceedings of the IEEE. 2013, Vol 101, Num 3, pp 698-722, issn 0018-9219, 25 p.Article

Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATIONRAUWERDA, Gerard K; HEYSTERS, Paul M; SMIT, Gerard J. M et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 1, pp 3-13, issn 1063-8210, 11 p.Article

A Medium-Grain Reconfigurable Architecture for DSP : VLSI Design, Benchmark Mapping, and Performance : CONFIGURABLE DESIGN-I: HIGH-LEVEL RECONFIGURATIONMYJAK, Mitchell J; DELGADO-FRIAS, José G.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 1, pp 14-23, issn 1063-8210, 10 p.Article

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGAABU TALIP, Mohamad Sofian; AKAMINE, Takayuki; OSANA, Yasunori et al.IEICE transactions on information and systems. 2012, Vol 95, Num 10, pp 2369-2376, issn 0916-8532, 8 p.Article

Encodage linéaire d'automates pondérés : Filtrage de motifs génomiques et application sur l'architecture prototype R-disk = One hot encoding of weighted automata: geometrical pattern filtering and application to the R-disk architectureGIRAUD, Mathieu; GUYETANT, Stéphane; LAVENIER, Dominique et al.TSI. Technique et science informatiques. 2005, Vol 24, Num 6, pp 703-724, issn 0752-4072, 22 p.Conference Paper

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